The invention generally relates to a buffer circuit, such as an input buffer, for example.
A buffer circuit, or buffer, is an electrical circuit that typically is used for purposes of preventing one circuit from electrically loading another circuit while passing a signal between the circuits. For example, an output buffer may be used to communicate a signal from a circuit to a load that has a low impedance while preventing the circuit from experiencing the large current fluctuations that are associated with driving a low impedance load.
Similarly, an input buffer may be used to, for example, receive a signal from a conductive line of a bus and provide an indication of the signal to digital circuitry that, in turn, processes the signal. The digital circuitry may not be capable of receiving the signal directly from the bus due to such factors as an incompatible voltage level of the bus line or a large capacitance of the bus line, as just a few examples.
A typical input buffer may include an amplifier that has input terminals for receiving the input signal and output terminals for furnishing an output signal that is indicative of the input signal. The amplifier or other circuitry of the buffer may be damaged if an input signal (such as an electrostatic discharge (ESD) signal, for example) is received by this circuitry when the input buffer is not powered up. For purposes of preventing this damage from occurring, the input buffer may include a pass gate that is coupled between an input terminal of the buffer and the input terminal of the amplifier. In this manner, the pass gate does not conduct and thus, blocks communication of the input signal when the input buffer is powered down, and the pass gate conducts when the input buffer is powered up.
As an example, the pass gate may be formed from an n-channel metal-oxide-semiconductor field-effect-transistor (NMOSFET) 7, a device that is depicted in FIG. 1. A drain terminal 5 of the NMOSFET 7 may function as the input terminal of the input buffer to receive an input signal to the input buffer, and a source terminal 8 of the NMOSFET 7 may be coupled to the input terminal of the amplifier. When the input buffer is powered up, a positive voltage is applied to a gate terminal 6 of the NMOSFET 7 to establish a sufficient positive gate-to-source voltage (called VGS) to cause the NMOSFET 7 to conduct and communicate the input signal to the amplifier. Typically, the VGS voltage is large enough to place the NMOSFET 7 in its linear resistive region, a region in which a voltage difference (called VDS) between the drain 5 and source 8 terminals is near zero volts. To keep the VGS voltage large enough to keep the NMOSFET 7 in the linear resistive region, a relatively large constant turn on voltage may be applied to the gate terminal 6 to accommodate fluctuations in the voltage of the source terminal 8 due to fluctuations in the input signal. In this manner, the VGS voltage decreases when the input signal increases. Unfortunately, the gate-to-drain voltage (called VGD) of the NMOSFET 7 also varies inversely with the level of the input signal and has a maximum gate-to-drain voltage may not be exceeded without damaging the NMOSFET 7. Therefore, this criteria limits the voltage level that is selected for the gate turn on voltage and thus, limits the permissible voltage swing of the input signal.
Thus, there is a continuing need for an arrangement that addresses one or more of the problems that are stated above.
In an embodiment of the invention, an input signal is communicated to an amplifier using a pass gate circuit. A control voltage is provided to the pass gate circuit, and the control voltage is regulated in response to a magnitude of the input signal.
Advantages and other features of the invention will become apparent from the following description, drawing and claims.